In recent years, an embedded system has become increasingly sophisticated and is required to operate a large number of applications (processes) concurrently. As a high-end processor for supporting such high functionality, a “multi-core processor” in which a plurality of processors are integrated is used. In the multi-core processor, a cache memory is generally provided with respect to each core (processor).
When a plurality of processes are started in the multi-core processor system, resource contention between the processes occurs. Here, a process is a unit of processing executed, and a single process consists of a plurality of tasks that are parallel executable (task is also called thread; hereinafter it is collectively called “task”). Resources include a processor, a cache memory, a bus bandwidth and the like. The resource contention between processes may cause reduction in system performance. In order to maintain the system performance even when the plurality of processes are started, it is necessary to appropriately distribute resources to the respective processes.
For example, it is necessary to appropriately distribute respective computational resources of the plurality of processors to the plurality of processes. Here, data used by tasks belonging to the same process are considered to be highly relevant with each other. Therefore, improvement in cache use efficiency is expected by assigning a plurality of tasks belonging to the same process to the same processor as much as possible. Conversely, if a plurality of tasks belonging to the same process are dispersively assigned to various processors, the cache use efficiency is reduced and thus the system performance is degraded.
The followings are known as techniques related to assignment of resources in a multi-core processor system.
Patent Literature 1 (Japanese Patent No. 3266029) discloses a dispatching method in a multi-core processor system. The multi-core processor system consists of a plurality of processor groups and a main memory shared by the plurality of processor groups. Each processor group includes a plurality of processors and a cache memory. Any processor in each processor group monitors a hit ratio of the cache memory of the each processor group. If the cache hit ratio is lowered, the processor migrates any task having been executed by the processor group to another processor group where the cache hit ratio is high. As a result, performance degradation as a whole system can be prevented.
Patent Literature 2 (Japanese Patent Publication JP-2007-316710) discloses a technique for improving throughput of a whole system in a multi-core processor system. With regard to each process group, a flag is set depending on degree of cooperative operation between processes (ON=high cooperation degree, OFF=low cooperation degree). In a case of high cooperation degree, reusability of data between the processes is high. Therefore, a process group whose flag is ON is occupied by one processor group. On the other hand, a process group whose flag is OFF is not occupied by a specific processor group but executed dispersively by a plurality of processor groups. As a result, performance of a whole system is improved.